12/29/2022 0 Comments Pld jed simulation![]() ![]() Although it seems my Uni had originally designed the experiment boards around the Intel 5C031 (= Altera EP310? 300-gate device). We'd used it with an Intel 5C600 - but could also use an Altera EP600 (both 600 gate devices, that were equivalent). So it's probably possible to manually at least produce some logic-equations based on EPLD architecture from that. ![]() SMF (State Machine File) However, iPLS did have an Edit JEDEC File option, which presented a graphical representation of the internal structure of the IC that let you examine the details of the Macrocells / comparing with datasheets to try make sense the bit-patterns in the Macrocell window. REP (Report File).Plus it seems you could also use its iSTATE compiler with a. JED JEDEC file for use by its built-in Logic Programming Software (LPS) It also produced a. LEF (Logic Equation File) Sum Of Products file (for use by its Functional Simulator) which it then reduced, determined resources and did design-fitting, producing the. ADF (Advanced Design File) describing the Boolean equations (as well as specifying the part / pin-usage / Turbo or Low Power etc) Its Logic Optimising Compiler converted this to a. I've dug out 1st yr Uni notes from >30yrs ago, on the first software I used: The (DOS) iPLS (Intel Programmable Logic System), as detailed in this AppNote Manual: (Where I noticed in a screen shot that it was (c) 1985 Intel & (c) 1985 Altera) JED file (Mostly just a large table of 1's and 0's) back to the original equations. I never realised you could disassemble a. ![]()
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |